A DIMM, or dual in-line memory module, comprises a series of dynamic random access memory incorporated circuits. This modules are mounted on a published circuit board and designed for usage in an individual computers, workstations and also servers. DIMMs began to change SIMMs (single in-line storage modules) together the predominant kind of memory module as Intel’s Pentium processors started to obtain market share.

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The main difference in between SIMMs and also DIMMs is that DIMMs have actually separate electric contacts on each side the the module, if the contact on SIMMs top top both sides are redundant. One more difference is that standard SIMMs have a 32-bit data path, while standard DIMMs have actually a 64-bit data path. Due to the fact that Intel’s Pentium has (as do several various other processors) a 64-bit bus width, it requires SIMMs set up in matched pairs in bespeak to finish the data bus. The processor would then accessibility the two SIMMs simultaneously. DIMMs were presented to eliminate this practice.


Two types of DIMMs: a 168-pin SDRAM module (top) and a 184-pin DDR SDRAM module (bottom). Keep in mind that the SDRAM module has two notches on the bottom edge, while the DDR1 SDRAM module has only one. Additionally note that both modules have actually 8 lamb chips, yet the reduced one has actually an unoccupied an are for a 9th.


The most common species of DIMMs are:

72-pin SO-DIMM (not the exact same as a 72-pin SIMM), offered for FPM DRAM and EDO DRAM100-pin DIMM, provided for press SDRAM144-pin SO-DIMM, used for SDR SDRAM168-pin DIMM, used for SDR SDRAM (less commonly for FPM/EDO theatre in workstations/servers)172-pin MicroDIMM, used for DDR SDRAM184-pin DIMM, offered for DDR SDRAM200-pin SO-DIMM, provided for DDR SDRAM and DDR2 SDRAM204-pin SO-DIMM, offered for DDR3 SDRAM214-pin MicroDIMM, offered for DDR2 SDRAM240-pin DIMM, offered for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM

Key positions


The various varieties of memory have actually different crucial positions that permit for stupid proof installation and also disallow not compatible memory species to be installed.

168-pin SDRAM

On the bottom leaf of 168-pin DIMMs there room 2 notches, and also the location of every notch identify a specific feature the the module.

The an initial notch is DRAM an essential position. It represents RFU (reserved future use), registered, and also unbuffered (in the order native left to center to appropriate position).The second notch is voltage key position. It represents 5.0V, 3.3V, and also Reserved (order as above).The top DIMM in the photo is an unbuffered 3.3V 168-pin DIMM. DIMM slots support likewise DDR1, 2, 3 RAM.


DDR, DDR2 and DDR3 all have actually a various pin-count, and different notch position.


A DIMM’s capacity and timing parameters may be figured out with Serial presence Detect (SPD), secondary chip which includes information around the module kind and timing for the memory controller to be configured correctly.

Error correction

ECC DIMMs room those that have actually extra data bits which have the right to be offered by the device memory controller to detect and correct errors. Over there are plenty of ECC schemes, however perhaps the most usual is single Error Correct, twin Error recognize (SECDED) which supplies an extra byte per 64-bit word. ECC modules usually lug a lot of of 9 instead of a multiple of 8 chips.


The number of ranks on any DIMM is the number of independent sets of DRAMs that deserve to be accessed because that the full data bit-width that the DIMM ie 64 bits. The ranks cannot it is in accessed at the same time as they share the very same data path. The physical layout of the theatre chips on the DIMM itself does no necessarily relate to the variety of ranks.

DIMMs are often referred to together “single-sided” or “double-sided” in referral to the ar of the memory devices or “chips” gift on just one or both sides of the DIMM published circuit board (PCB). This terms may cause confusion as they execute not necessarily relate to how the DIMMs room logically arranged or accessed.

For example, ~ above a single-rank DIMM that has actually 64 data bits of I/O pins, over there is just one collection of DRAMs that room turned on to journey a check out or obtain a create on all 64 bits. In most digital systems, memory controllers are designed to accessibility the full data bus broad of the memory module at the exact same time.

On a 64-bit (non-ECC) DIMM made through two ranks, there would certainly be two sets of theatre that could be accessed at different times. Only among the ranks deserve to be accessed at a time, since the plays data bits room tied with each other for two lots on the DIMM (Wired OR). Ranks space accessed v chip selects (CS). For this reason for a 2 rank module, the 2 DRAMs v data bits tied together might be accessed through a CS per DRAM (e.g. CS0 goes to one dram chip and also CS1 goes to the other). DIMMs are currently being commonly manufactured with up to 4 ranks every module.

Consumer DIMM vendors have recently started to identify between single and dual ranked DIMMs. JEDEC chose that the state “dual-sided,” “double-sided,” or “dual-banked” were no correct when applied to registered DIMMs.


Most DIMMs are built using “x4” (by 4) memory chips or “x8” (by 8) memory chips through 9 chips per side. “x4” or “x8” describe the data width of the plays chips in bits.

In the instance of the “x4”-registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to attend to both political parties at the very same time to read or write the data that needs. In this case, the two-sided module is single-ranked.

For “x8”-registered DIMMs, each side is 72 bits wide, for this reason the memory controller only addresses one side at a time (the two-sided module is dual-ranked).


For various technologies, there are certain bus and machine clock frequencies that space standardized. There is also a determined nomenclature because that each of this speeds because that each type.

SDR SDRAM DIMMs – These an initial synchronous registered theatre DIMMs had the exact same bus frequency for data, address and control lines.

PC66 = 66 MHzPC100 = 100 MHzPC133 = 133 MHz

DDR SDRAM (DDR1) DIMMs – DIMMs based on dual Data rate (DDR) DRAM have data but not the strobe at twin the rate of the clock. This is accomplished by clocking top top both the rising and falling sheet of the data strobes.

PC1600 = 200 MHz data & strobe / 100 MHz clock for attend to and controlPC2100 = 266 MHz data & strobe / 133 MHz clock for resolve and controlPC2700 = 333 MHz data & strobe / 166 MHz clock for address and controlPC3200 = 400 MHz data & strobe / 200 MHz clock for attend to and control

DDR2 SDRAM DIMMs – DIMMs based on dual Data rate 2 (DDR2) DRAM also have data and data strobe frequencies at dual the rate of the clock. This is accomplished by clocking top top both the rising and falling leaf of the data strobes. The strength consumption and voltage that DDR2 is significantly lower than DDR(1) in ~ the same speed.

PC2-3200 = 400 MHz data & strobe / 200 MHz clock for deal with and controlPC2-4200 = 533 MHz data & strobe / 266 MHz clock for resolve and controlPC2-5300 = 667 MHz data & strobe / 333 MHz clock for resolve and controlPC2-6400 = 800 MHz data & strobe / 400 MHz clock for attend to and controlPC2-8000 = 1000 MHz data & strobe / 500 MHz clock for resolve and controlPC2-8500 = 1066 MHz data & strobe / 533 MHz clock for attend to and controlPC2-9600 = 1200 MHz data & strobe / 600 MHz clock for attend to and control

DDR3 SDRAM DIMMs – DIMMs based on dual Data price 3(DDR3) DRAM have data and strobe frequencies at dual the rate of the clock. This is achieved by clocking ~ above both the rising and also falling edge of the data strobes. The strength consumption and voltage of DDR3 is reduced than DDR2 the the same speed.

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PC3-6400 = 800 MHz data & strobe / 400 MHz clock for deal with and controlPC3-8500 = 1066 MHz data & strobe / 533 MHz clock for deal with and controlPC3-10600 = 1333 MHz data & strobe / 667 MHz clock for attend to and controlPC3-12800 = 1600 MHz data & strobe / 800 MHz clock for address and controlPC3-16000 = 2000 MHz data & strobe / 1000 MHz clock for address and control

Form factors

Several form factors are commonly used in DIMMs. Single Data price (SDR) SDRAM DIMMs frequently came in two key heights: 1.7-inch and 1.5-inch. Once 1U rackmount servers started coming to be popular, these type factor Registered DIMMs had to plug into angled DIMM sockets to fit in the 1.75″ high box. To minimize this issue, the following standards the DDR DIMMs were produced with a “Low Profile” (LP) height of ~1.2″. These fit into vertical DIMM sockets for a 1U platform. With the introduction of tongue servers, the LP kind factor DIMMs have actually once again been frequently angled to fit in these space-constrained boxes. This led to the advance of the very Low file (VLP) type factor DIMM through a height of ~.72″ (18.3 mm). The DDR3 JEDEC traditional for VLP DIMM height is 18.75mm. These will certainly fit vertically in ATCA systems. Various other DIMM kind factors encompass the SO-DIMM, the Mini-DIMM and the VLP Mini-DIMM.